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74VHCT16373A
16-BIT D-TYPE LATCH WITH 3-STATE OUTPUTS NON INVERTING
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HIGH SPEED: tPD = 5.0 ns (TYP.) at VCC = 5V LOW POWER DISSIPATION: ICC = 4 A (MAX.) at TA=25C COMPATIBLE WITH TTL OUTPUTS: VIH =2V (MIN.) VIL = 0.8 (MAX.) POWER DOWN PROTECTION ON INPUTS SYMMETRICAL OUTPUT IMPEDANCE: |IOH| = IOL = 8 mA (MIN) BALANCED PROPAGATION DELAYS: tPLH tPHL OPERATING VOLTAGE RANGE: VCC(OPR) = 4.5V to 5.5V PIN AND FUNCTION COMPATIBLE WITH 74 SERIES 16373 IMPROVED LATCH-UP IMMUNITY LOW NOISE: VOLP = 0.9V (MAX.)
TSSOP
ORDER CODES
PACKAGE TSSOP TUBE T&R 74VHCT16373ATTR
PIN CONNECTION
DESCRIPTION The 74VHCT16373A is an advanced high-speed CMOS 16 BIT D-TYPE LATCH with 3 STATE OUTPUTS NON INVERTING fabricated with sub-micron silicon gate and double-layer metal wiring C2MOS technology. These 16 bit D-TYPE latches are byte controlled by two latch enable inputs (nLE) and two output enable inputs(nOE). While the nLE input is held at a high level, the nQ outputs will follow the data (D) inputs. When the nLE is taken LOW, the nQ outputs will be latched at the logic level of D data inputs. When the (nOE) input is low, the nQ outputs will be in a normal logic state (high or low logic level); when nOE is at high level ,the outputs will be in a high impedance state. Power down protection is provided on all inputs and 0 to 7V can be accepted on inputs with no regard to the supply voltage. This device can be used to interface 5V to 3V. All inputs and outputs are equipped with protection circuits against static discharge, giving them 2KV ESD immunity and transient excess voltage.
February 2003
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74VHCT16373A
INPUT EQUIVALENT CIRCUIT
PIN DESCRIPTION
PIN No 1 SYMBOL 1OE NAME AND FUNCTION
IEC LOGIC SYMBOLS
3 State Output Enable Input (Active LOW) 2, 3, 5, 6, 8, 9, 1Q0 to 1Q7 3-State Outputs 11, 12 13, 14, 16, 17, 2Q0 to 2Q7 3-State Outputs 19, 20, 22, 23 3 State Output Enable 24 2OE Input (Active LOW) 25 2LE Latch Enable Input 36, 35, 33, 32, 2D0 to 2D7 Data Inputs 30, 29, 27, 26 47, 46, 44, 43, 1D0 to 1D7 Data Inputs 41, 40, 38, 37 48 1LE Latch Enable Input 4, 10, 15, 21, GND Ground (0V) 28, 34, 39, 45 7, 18, 31, 42 VCC Positive Supply Voltage
TRUTH TABLE
INPUTS OE H L L L LE X L H H D X X L H OUTPUT Q Z NO CHANGE * L H
X : Don`t Care Z : High Impedance * : Q outputs are latched at the time when the LE input is taken low logic level.
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74VHCT16373A
LOGIC DIAGRAM
This logic diagram has not to be used to estimate propagation delays
ABSOLUTE MAXIMUM RATINGS
Symbol VCC VI VO IIK IOK IO Supply Voltage DC Input Voltage DC Output Voltage DC Input Diode Current DC Output Diode Current DC Output Current Parameter Value -0.5 to +7.0 -0.5 to +7.0 -0.5 to VCC + 0.5 - 20 20 25 75 -65 to +150 300 Unit V V V mA mA mA mA C C
ICC or IGND DC VCC or Ground Current Tstg Storage Temperature TL Lead Temperature (10 sec)
Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied
RECOMMENDED OPERATING CONDITIONS
Symbol VCC VI VO Top dt/dv Supply Voltage Input Voltage Output Voltage Operating Temperature Input Rise and Fall Time (note 1) (Vcc= 5.00.5V) Parameter Value 4.5 to 5.5 0 to 5.5 0 to VCC -55 to 125 0 to 20 Unit V V V C ns/V
1) VIN from 0.8V to 2.0V
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74VHCT16373A
DC SPECIFICATIONS
Test Condition Symbol Parameter VCC (V) 4.5 to 5.5 4.5 to 5.5 4.5 4.5 4.5 4.5 5.5 0 to 5.5 5.5 IO=-50 A IO=-8 mA IO=50 A IO=8 mA VI = VIH or VIL VO = VCC or GND VI = 5.5V or GND VI = VCC or GND TA = 25C Min. 2 0.8 4.4 3.94 0.0 0.1 0.36 0.25 0.1 4 4.5 4.4 3.8 0.1 0.44 2.5 1 40 Typ. Max. Value -40 to 85C Min. 2 0.8 4.4 3.7 0.1 0.55 2.5 1 40 Max. -55 to 125C Min. 2 0.8 Max. V V V V A A A Unit
VIH VIL VOH VOL IOZ
High Level Input Voltage Low Level Input Voltage High Level Output Voltage Low Level Output Voltage High Impedance Output Leakage Current Input Leakage Current Quiescent Supply Current
II ICC
AC ELECTRICAL CHARACTERISTICS (Input tr = tf = 3ns)
Test Condition Symbol Parameter VCC (V) 5.0(*) 5.0(*) 5.0(*) 5.0(*) 5.0(*) 5.0(*) 5.0(*) 5.0
(**)
Value TA = 25C Min. Typ. 5.0 6.0 5.5 6.2 5.2 6.5 6 7 5 4 1 Max. 8.5 9.5 8.5 9.5 9.5 10.5 10.2 11.2 -40 to 85C Min. 1 1 1 1 1 1 1 1 5 4 1 1.. 1.5 Max. 9.5 10.5 9.5 10.5 10.5 11.5 11.0 12.0 -55 to 125C Min. 1 1 1 1 1 1 1 1 5 4 1 1.5 Max. 9.5 10.5 9.5 10.5 10.5 11.5 11.0 12.0
Unit
CL (pF) 15 50 15 50 15 50 15 50
tPLH tPHL tPLH tPHL tPZL tPZH tPLZ tPHZ tw ts th tOSLH tOSHL
Propagation Delay Time LE to Qn Propagation Delay Time Dn to Qn Output Enable Time Output Disable Time Pulse Width (LE) HIGH Setup Time Dn to LE HIGH or LOW Hold Time Dn to LE HIGH or LOW Output to Output Skew time (note 1)
ns
ns
ns ns
5.0(*) 5.0(*) 5.0(*) 5.0(*) 50
ns ns ns ns
(*) Voltage range is 5.0V 0.5V (Note 1 : Parameter guaranteed by design. tsoLH = |tpLHm - tpLHn|, tsoHL = |tpHLm - tpHLn|
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CAPACITIVE CHARACTERISTICS
Test Condition Symbol Parameter VCC (V) TA = 25C Min. Typ. 4 6 5.0 fIN = 10MHz 21 Max. 10 Value -40 to 85C Min. Max. 10 -55 to 125C Min. Max. 10 pF pF pF Unit
CIN COUT CPD
Input Capacitance Output Capacitance Power Dissipation Capacitance (note 1)
1) CPD is defined as the value of the IC's internal equivalent capacitance which is calculated from the operating current consumption without load. (Refer to Test Circuit). Average operating current can be obtained by the following equation. ICC(opr) = CPD x VCC x fIN + ICC/n (per Latch)
DYNAMIC SWITCHING CHARACTERISTICS
Test Condition Symbol Parameter VCC (V) 5.0 TA = 25C Min. Typ. 0.6 -0.9 CL = 50 pF 3.5 -0.6 Max. 0.9 V Value -40 to 85C Min. Max. -55 to 125C Min. Max. Unit
VOLP VOLV VIHD
VILD
Dynamic Low Voltage Quiet Output (note 1, 2) Dynamic High Voltage Input (note 1, 3) Dynamic Low Voltage Input (note 1, 3)
5.0
V
5.0
1.5
V
1) Worst case package. 2) Max number of outputs defined as (n). Data inputs are driven 0V to 5.0V, (n-1) outputs switching and one output at GND. 3) Max number of data inputs (n) switching. (n-1) switching 0V to 5.0V. Inputs under test switching: 5.0V to threshold (V ILD), 0V to threshold (VIHD), f=1MHz.
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74VHCT16373A
TEST CIRCUIT
TEST tPLH, tPHL tPZL, tPLZ tPZH, tPHZ
CL = 15/50 pF or equivalent (includes jig and probe capacitance) RL = R1 = 1K or equivalent RT = ZOUT of pulse generator (typically 50)
SWITCH Open VCC GND
WAVEFORM 1 : LE TO Qn PROPAGATION DELAYS, LE MINIMUM PULSE WIDTH, Dn TO LE SETUP AND HOLD TIMES (f=1MHz; 50% duty cycle)
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WAVEFORM 2: OUTPUT ENABLE AND DISABLE TIME (f=1MHz; 50% duty cycle)
WAVEFORM 3 : PROPAGATION DELAY TIME (f=1MHz; 50% duty cycle)
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74VHCT16373A
TSSOP48 MECHANICAL DATA
mm. DIM. MIN. A A1 A2 b c D E E1 e K L 0 0.50 6.0 0.5 BSC 8 0.75 0 0.020 0.17 0.09 12.4 8.1 BSC 6.2 0.236 0.0197 BSC 8 0.030 0.05 0.9 0.27 0.20 12.6 0.0067 0.0035 0.488 0.318 BSC 0.244 TYP MAX. 1.2 0.15 0.002 0.035 0.011 0.0079 0.496 MIN. TYP. MAX. 0.047 0.006 inch
A
A2 A1 b e K c L E
D
E1
PIN 1 IDENTIFICATION
1
7065588C
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Tape & Reel TSSOP48 MECHANICAL DATA
mm. DIM. MIN. A C D N T Ao Bo Ko Po P 8.7 13.1 1.5 3.9 11.9 12.8 20.2 60 30.4 8.9 13.3 1.7 4.1 12.1 0.343 0.516 0.059 0.153 0.468 TYP MAX. 330 13.2 0.504 0.795 2.362 1.197 0.350 0.524 0.067 0.161 0.476 MIN. TYP. MAX. 12.992 0.519 inch
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Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. (c) The ST logo is a registered trademark of STMicroelectronics (c) 2003 STMicroelectronics - Printed in Italy - All Rights Reserved STMicroelectronics GROUP OF COMPANIES Australia - Brazil - Canada - China - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan - Malaysia - Malta - Morocco Singapore - Spain - Sweden - Switzerland - United Kingdom - United States. (c) http://www.st.com
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